Electrical supervisory control and data acquisition system

ABSTRACT

An electrical control system which comprises: a master station (2) and a plurality of receiver stations (4) connected thereto by a bus, (6), the master station including generating means (20, 22) for generating control signals (18) which are applied to said bus and to which said receiver stations are responsive, the control signals comprising a repetitive series of signal frames, each frame including a reset pulse (18) and a plurality of other pulses, the master station including control means (14) which causes selectable alteration of a characteristic of said other pulses, and wherein each of said receiver stations is addressed following receipt of a predetermined number of said other pulses, said receivers being responsive to said selectable characteristic of the other pulses whereby information is transmitted to addressed receiver stations in accordance with operation of said control means, whereby data and address information are constituted in the same pulses. The system may further include circuitry which permits the receiver being addressed to transmit information to the master station. The system would have wide applications, for instance, in nurse paging systems in hospitals.

This is a continuation-in-part of co-pending application Ser. No.326,627 filed Dec. 2, 1981, abandoned.

This invention relates to a system for remote control of a plurality ofelectrical devices, the system having a master control station whichgoverns the operation of a plurality of receiver stations which in turnare coupled to control and/or monitor electrical devices. The electricaldevices could comprise any device that may be controlled or monitored byelectrical signals. For instance, the electrical devices could compriseair conditioning controls, lighting switches, safety devices, displays,burglar alarms or the like.

U.S. Pat. No. 4,227,181 to Brittain discloses a time division multiplexcommunication system whereby the sync signal is voltage amplitudemodulated, command and tell back signals are pulse width modulated andeach time slot is assigned as either a command or tell back time slot.

U.S. Pat. No. 3,905,008 to Hagemann discloses an electronic signallingsystem from a consul station to a plurality of sensing units wherebyvoltage polarity and duration are used for signalling. The position ofthe sensing unit determines its address.

Other patents of interests are Australian Pat. No. 498,812 andSpecification No. 22657/77 and U.K. Pat. No. 2,041,592A.

According to the present invention there is provided an electricalcontrol system comprising a master station and a plurality of receiverstations connected thereto by a bus, said master station includinggenerating means for generating control signals which are applied tosaid bus and to which said receiver stations are responsive, saidcontrol signals comprising a repetitive series of signal frames eachframe including a reset pulse and a plurality of other pulses, saidmaster station including control means which causes selectablealteration of a characteristic of said other pulses and wherein each ofsaid receiver stations is addressed following receipt of a predeterminednumber of said other pulses, said receivers being responsive to saidselectable characteristic of the other pulses whereby information istransmitted to addressed receiver stations in accordance with operationof said control means. Said receiver station when addressed also variesthe bus impedance in accordance with its status and input.

In the preferred arrangement each signal frame commences with a resetpulse which is then followed by a predetermined or varying number ofsaid other pulses which are used both for addressing the variousreceivers and for transmitting information to the various receivers.

Preferably further, each receiver station has at least one input, oneoutput and three electrical impedances which are coupled to or notcoupled to the bus line in accordance with the conditions of the outputstatus, the input and receiver status at that receiver during thesignalling period which occurs following addressing of that receiver.The master station includes a monitor coupled to the bus line and beingoperable to determine the impedance coupled to the bus line and assignlogical value to the output status, input and status of that receiverresponsive to that address, in accordance with the impedance coupled tothe bus line. In the preferred arrangement, the three electricalimpedances are resistances of value R for the receiver status, R/2 forthe input and R/4 for output status.

In the preferred arrangement the master station transmits command outputinformation to the selected remote receiver by varying the duration ofthe period to the next address pulse. In the alternative arrangement,the master station transmits command output information to the selectedremote receiver by varying the number of zero pulses compared to thereset and address pulses which are at a non zero datum, during theperiod before the next address pulse.

The invention will now be further described with reference to theaccompanying drawings, in which:

FIG. 1 is a schematic representation of a system in accordance with theinvention;

FIG. 2 is a block diagram of the master station;

FIG. 3 illustrates various signal waveforms useful in understanding theoperation of the system;

FIG. 4 is a block diagram of the preferred remote receiver station;

FIG. 5 is a detailed schematic diagram of the preferred master controlstation bus interface circuitry;

FIG. 6 is a detailed schematic diagram of the preferred receiverstation;

FIG. 7 illustrates various signal wave forms useful in understanding theoperation of the receiver station; and

FIG. 8 illustrates schematically one example of utilization of thesystem;

FIG. 9 is a schematic diagram of the control station;

FIG. 10 is a flow chart of the microprocessor program in the controlstation;

FIG. 11 is a detailed schematic diagram of the alternative remotereceiver station;

FIG. 12 is a detailed schematic diagram of the modified master stationfor the alternative remote receiver station;

FIG. 13 illustrates various signal waveform useful in understanding theoperation of the alternative remote receiver station.

Referring first to FIG. 1, there is illustrated a system having a masterstation 2, a plurality of receiver stations 4 each connected in parallelto the master station 2 by means of a bus line 6 the bus line 6preferably comprises a single pair of wires. The master station can beset manually or otherwise at its inputs 3 so as to generate controlsignals which control the operation of various receiver stations 4. Thereceiver stations 4 may have outputs 8 (see FIG. 4) which preferablycomprise an output interface which is coupled to control electricaldevices 9 such as lights, air conditioning, etc. The receivers may alsohave inputs 10 which are interfaces to sensors (not shown) which canindicate the state of some parameter being monitored. For instance, thesensor may detect smoke, heat, or the states of switches.

The system is also arranged to transmit signals from the receiverstations 4 back to the master station 2 so as to produce a response atthe output of 12 of the master station 2 and/or at output of otherreceiver stations 4.

As shown in FIG. 2, the master station 2 includes master controlcircuitry 14 which generates control signals to be coupled to the busline 6 to which the receiver stations 4 are responsive. The controlcircuitry 14 also includes means responsive to signals generated at thereceivers 4.

FIG. 3 illustrates a control signal waveform 16 applied to the bus 6 bythe circuitry at the master station 2. The control signal comprises arepetitive sequence of frames each of which is initiated by a resetpulse 18. The pulse is generated from a voltage source 20 connected tothe bus 6 via switch 22. The voltage source 20 also supplies power tothe master station circuitry and all the receiver stations 4 via the bus6. The state of switch 22 is controlled by the control circuitry 14.

The reset pulses 18 are distinguished from other pulses by theirduration (T₁ -T₀) which is controlled so as to be significantly longerthan the other pulses in the frame. In the preferred arrangement, theduration of (T₁ -T₀) is about 10 milliseconds whereas the remainingpulses in the frame such as (T₃ -T₁) are about 1 millisecond induration. To define the various pulses in the frame, the circuitry 14maintains the power switch 22 disconnected and then reconnects thevoltage source 20 to the bus 6 causing the voltage on the bus line torise to its high level V₁. During the periods when the voltage source 20is disconnected, such as the period (T₂ -T₁), a current source 36maintains a voltage V₂ on the bus 6 via diode 38, the voltage V₂ beinglower than the voltage V₁. A current monitor 40 monitors the currentdraw by the bus 6 during the period the bus voltage is at V₂. Thisenables information relating to the receivers to be monitored bymonitoring the level of current drawn. The output of the monitor 40 is avoltage proportional to the current drawn. The current source 36 andcurrent monitor 40 can be replaced by a voltage source and a voltagemonitor respectively. The duration of the periods in which the voltagesource 20 is disconnected for example (T₂ -T₁) or (T₈ -T₇) is controlledby the circuitry to be of a short period T or long period, said 2T, sothat the selection of periods T or 2T can be used as a signallingfunction, to the various receivers as seen in diagram 87 in FIG. 3. Theperiod T is preferably 0.3 milliseconds.

Each of the receivers 4 has an address store 30 which has the addressinformation representative of the particular receiver. Each receiverincludes receiver logic circuitry 32 which is responsive, among otherthings, to the rising edges 28 in the waveform 16 applied to the bus 6by the master station 2. The receivers each effectively counts thenumber of such rising edges following each reset pulse 18 and this countis compared to an address number (which is different for each of thereceivers) in its address store 30 and when they are equal theparticular receiver identifies that it has been addressed by the masterstation 2. By this means the master station 2 can address each of thereceiver seriatum. Thus the address information for all the receivers iseffectively accomplished by means of a simple counting of the risingedges 28 following each reset pulse and matching the count with theaddress number in the address stores 30 of the receivers.

When a particular receiver identifies that it has been addressed by themaster station 2 its logic circuitry 32 is arranged to connect one ormore of electrical loads or resistors 68, 69 and 70 to the bus 6. In thepreferred arrangement the load 68 is connected every time the receiversenses that it has been addressed by the master station 2, but theconnection of loads 69 and 70 is dependent upon conditions at thereceiver. For example, electrical load 69 is connected or not connectedto the bus 6 in accordance with the state of the input 10 and electricalload 70 is connected or not connected to the bus 6 in accordance to thestatus 11 of the output 8, the status being indicated by an outputstatus circuit 11 responsive to the output 8 and/or device 9, as seen indiagram 89 in FIG. 3.

The loads 68, 69 and 70 are disconnected from the bus 6 after the nextrising edge 28 is detected.

The receiver being addressed also detects the duration in which the bus6 is at voltage level V₂, i.e. until the occurrence of the next risingedge 28, for instance the period (T₂ -T₁). The receiver output 8 iscontrolled by its logic circuitry 32 to generate a logical value inaccordance if whether or not the duration is greater or less than thepredetermined period set by the control circuitry of the master control2. This set time has a value between T and 2T preferably the mid-value,and therefore the set time is preferably 0.45 milliseconds.

Referring once again to FIG. 4, each receiver 4 has a capacitor 65 whichis charged via diode 64 to voltage V₁ when the voltage source 20 isconnected to the bus 6. The charge on the capacitor 65 supplies power tothe receiver circuit when voltage source 20 is disconnected from the bus6. Each receiver also has a comparator 63 which has a reference voltageapplied to one of its inputs 50. In the preferred arrangement, thevoltage V₁ is about 12 V and voltage V₂ is about 5 V. Therefore, thereference voltage is chosen to be about 8.5 V. The comparator 63functions to translate the voltage waveform on the bus 6 so as to besuitable for the receiver logic 32. In the preferred arrangement,receiver logic 32 consists of CMOS devices which inherently have highnoise immunity.

At the master station 2 the monitor 40 monitors the level of currentflowing in the bus during the periods when the voltage source 20 isdisconnected from the bus 6 and in this way information from thereceivers is transmitted to the master station. The values of the loads68, 69, 70 are chosen such that if load 68 only is connected across thebus 6, it would cause a current I to flow, load 69 alone would cause acurrent of 2I whereas load 70 alone would cause a current of 4I, whichwould correspond to an output of I volt, 2I volt and 4I volt at themonitor 40, as represented by waveform 80 in FIG. 3.

One example of a possible data transmission mode is illustrated in FIG.3. As is apparent from the series of diagrams in that figure, if theoutput of monitor 40 is zero, corresponding to the condition that, noneof the electrical loads 68, 69 and 70 is connected to the bus 6 afterone of the receivers should have been addressed, that condition wouldindicate a fault in or at the addressed receiver. For instance in FIG.3, the receiver R_(o), has been shown as having produced a zero responseat the monitor 40 indicating that the receiver is faulty.

During the time period T₃ to T₄ during which the receiver R₁ is beingaddressed the output of monitor 40 is I volt, as seen in diagram 80. Thestation 2 interprets that the receiver R₁ has a logical 0 at its input10 and output status of logical 0, as seen in diagrams 83 and 85respectively. The receiver R₁ interprets its output 8 to be set tological 0. During the time period T₅ to T₆ the output of monitor 40 is3I volt. The master station 2 interprets that the receiver R₂ has alogical 1 at its input 10 and output status of logical 0. The receiverR₂ interprets that its output 10 is to be set to logical 0. Diagram 81shows correct interpretration of receiver status. During the time periodT₇ to T₈ the output of monitor 40 is 5I volt. The master station 2interprets that the receiver R₃ has at its input 10 logical 0 and outputstatus of logical 1. The receiver R₃ interprets that its output is to beset to logical 1. During the time period T₉ to T₁₀ the output of monitor40 is 7I volt. The master station interprets that the receiver R₄ has atits input 10 logical 1 and output status of logical 1. The receiver R₄interprets that its output 8 is to be set to logical 1. During timeperiod T₁₁ to T₁₂ the output of monitor 40 is 3I volt. The masterstation interprets that the receiver R₅ has at its input 10 logical 1and output status of logical 0. The receiver interprets that its output8 is to be set to logical 1. In this case, the receiver R₅ output isassigned a logical 1 and the master station interprets that the outputstatus is logical 0, the master station would indicate a fault at theoutput 8 of receiver R₅ or a fault at the electrical device controlledby receiver R₅ if, during the previous signal frame, receiver R₅ output8 is also assigned a logical 1 and the output response time which is thetime it takes the output to change state is zero. If the response timeis non-zero then at least this response time must lapse after the framein which the output is first assigned a logical 1 before a fault wouldbe indicated. This shows that when the master station 2 first detected adifference in the output status and the output assigned to a particularreceiver, it must wait at least one signal frame time plus the outputresponse time before it indicates a fault at the output 8 of thatparticular receiver. The signal interpretation continues until the nextreset pulse 18 and then the interpretation repeats again.

In the preferred arrangement for the master station 2, as shown in FIG.5, the input 3 and output 12 comprises a VDU terminal whereas thecontrol circuitry 14 comprises a microprocessor system and need not bedescribed in detail herein. The system 14 generates a waveform 16 asillustrated in FIG. 3 and its output port 50 of 0-5 volts amplitude. Theinput 51 is a parallel input port of the microprocessor system 14. Whenthe output 50 is at 5 volts it turns on transistors 52 and 53 whichconnect the 12 volts supply from the supply 20 to the bus 6. When theoutput 50 is at 0 volts, the transistors 52 and 53 are turned offremoving the 12 volts supply from the bus 6. At this period, the voltageat the bus 6 is maintained at 5 volts by an amplifier 54 coupled viaresistor 56 and diode 38, the waveform being illustrated in FIG. 3 aswaveform 16, the voltage V₁ and V₂ corresponding to the 12 and 5 voltlevels. The amplifier 54 maintains a voltage of 5.6 volts at the point55 at all times. When one or more of the resistors 68, 69 and 70 of theaddressed receiver 4 are connected to the bus 6, a current is drawn fromthe amplifier 54 via resistor 56 and diode 38 causing the voltage atpoint 57 to raise above 5.6 volts depending upon the combined impedanceof the resistors 68, 69 and 70 which are actually connected to the bus 6at the addressed receiver. The voltage across the resistor 56 isbuffered and is amplified by the amplifier 58 before being applied tothe input of an analogue to digital converter 59. The output of theconverter 59 is connected to input 51 of the microprocessor system 14.The preferred value of the resistor 56 is 100 ohms.

In the preferred arrangement for the receiver 4, as shown in FIG. 6, theresistors 68, 69 and 70 are connected across the bus 6 via transistors71, 72 and 73, respectively. The reference voltage of comparator 63 ismaintained at 8.2 volts by a zener diode 74. The output waveform atpoint 67 us illustrated as waveform 100 in FIG. 7. The output of thecomparator 63 is applied to the input of a decade counter/divider 75which may comprise a CMOS device CD4017 and to a second decadecounter/divider 76 which counts the number of rising edges 28 in thewaveform 16 after being reset in accordance with the voltage on acapacitor 79. The voltage at the capacitor 79 will only attain therequired level for resetting of the counter/dividers 75 and 76 duringthe reset period 18 of the waveform 16. The preferred value of theresistor 78 is 100k ohm and the value of the resistor 79 is 0.1 μF. Inthe address store 30, input to NAND gate 90 are from counter/dividers 75and 76 via two 10-pole switches 91 and 92 which are set to a differentvalue in accordance with the number of the receiver. In the illustratedarrangement, the switches 91 and 92 are set to indicate receiver havingthe address "46". The output 94 of NAND gate 90 is at zero volts onlybetween the 46th and 47th rising edges 28 after the reset pulse, as isillustrated in waveform 102 in FIG. 7.

When the output 94 is at 0 volts, transistor 71 is turned on via aninverter 91, thus connecting resistor 68 across the bus 6. When theoutput 94 and switch 10 are both zero volts, as shown in FIG. 7, theresistor 69 is connected across the bus 6 via NOR gate 92 and transistor72.

When the output 94 is at 0 volts and the relay 9 is on, the resistor 70will additionally be connected across the bus 6 via NOR gate 93 andtransistor 73.

The output from the comparator 63 is also connected to the trigger inputof a monostable multivibrator 95 and data input of flip-flop 96. Theoutput 94 is also connected to the inhibit input of the monostablemultivibrator 95. The output of monostable multivibrator 95 comprises apulse of 0.45 ms duration when it is triggered by the falling edge ofthe waveform 100 (i.e. output from the comparator 63) while its inhibitis at 0 volts, as illustrated by waveform 103 in FIG. 7.

The signal at data input of flip-flop 96 is clocked by the falling edgeof waveform 103. If the period when the bus 6 is at 5 volts is T then atthe falling edge of the waveform 103, the data input would be at a highlevel, therefore the inverted output 97 of flip-flop 96 would be 0 voltsas illustrated by waveform 104 in FIG. 7. For the receiver 4 withaddress "47" the output 97 of flip-flop 96 is at a high voltage levelsince the period when the bus 6 is at 5 volts is to T, as illustrated inwaveform 107. When the inverted output 97 is at a high level, the relaydevice 9 is turned on via transistor 8, as shown in FIG. 6. Thewaveforms 105 and 106 correspond to the waveforms 102 and 103 exceptthat they would be relevant to the receiver with address 47.

Referring to FIG. 9, the VDU terminal display information accepts inputfrom its keyboard and functions as interface between operator and the8085 CPU. The timer provides the accurate timing required to generatethe signal at the bus 6, via an interrupt input to the 8085 CPU at theend of the timing period. A flow chart of the program in program memoryis illustrated in FIG. 10.

In FIG. 10, R(N) represent remote receiver with address N and NMAX asthe highest address. In the preferred arrangement, command output 0 isachieved by holding bus 6 at voltage V2 and T period instead of 2Tperiod for command output 1 before the next address pulse.

FIGS. 11, 12 and 13 illustrates an alternative arrangement fortransmitting command output information from the master station to theselected receiver station by varying the number of zero pulses beforethe next address pulse at bus 6. Referring to the alternative receiverstation as shown in FIG. 11, the PMOS transistor 81 and Schmitt trigger82 replaces the comparator 63 and zener 74 of FIG. 6. The NMOStransistor 82 and Schmitt trigger 84 and 83 decode the zero pulse at bus6. The voltage level at bus 6 is illustrated by waveform 110 and thesignal at point 99 is shown by waveform 111. The decode counter/divider87 counts the number of zero pulses between two address pulses is resetby the address pulses via delay buffer 86. The J-K flip flop 89 isclocked via OR Gate 88. Waveform 112, 114 and 116 is the output waveformof OR Gate 88 for receiver station 46, 47 and 49 respectfully. Theoutput at point 97 is dependent on the state of the outputs "1" and "2"of decode counter/divider 87 as illustrated by waveform 113, 115 and 117for receiver station 46, 47 and 49 respectfully.

FIG. 12 has an additional transistor 48 and output 49 from controlstation compared to FIG. 5. Normally output 49 is at 0 volt. A pulsevoltage at 49 during the period between two address pulses would producea zero at bus 6.

FIG. 8 shows a simple practical utilization of the invention. Inparticular, FIG. 4 shows a receiver 4 which is one of a plurality ofreceiver units which could be located beside patients in a hospitalward, all of the receivers 4 being connected in parallel across the bus6 as indicated in FIG. 1. In this arrangement, the input 10 could takethe form of a press button which is activated when the patient requiresthe attention of a nurse. Activation of the press button would produce aresponse at the output of the master station 2. Such response could bein the form of a visual and/or audible alarm so that the appropriateaction can be taken. As a further enhancement, the receivers 4 may havetheir outputs 8 in the form of a relay coil which operates a pair ofcontacts as shown. One of the contacts closes a circuit 2 to aloudspeaker which constitutes the electrical device 9 being controlled.The nurse can then speak to the patient through the loudspeaker. Thesecond pair of contacts 11 simply monitors the fact that the relay coilhas operated and therefore ensures that communication has taken place tothe patient.

Many variations may of course be included in the basic system describedso far, so as to reduce the effects of noise in the bus 6 and/or toenhance the basic system. Some of the variations are:

(1) to reduce or eliminate the effects of noise in the bus 6, thereceivers 4 could be arranged such that they must receive in a givennumber of consecutive signal frames, preferably at least 2, to changetheir outputs before their outputs 8 change. In the same way, the masterstation 2 must receive in a given number of consecutive signal frames,preferably at least 2, so that a particular receiver status, its input10 and/or output status changes, before it interprets the change andperforms the required functions.

In addition, the waveform at input 67 of the circuitry 32 can also bearranged to have slow rise and fall times and the circuitry 32 includesa Schmitt trigger buffer so that any high frequency noise (for instancegreater than 10 KHz) would not affect the operation of the receiverlogic 32. In most applications, these enhancements would be essentialwhere reliable operation was of vital importance.

(2) The power supply to some or all the receivers 4 can be from anothersource other than from the bus 6.

(3) A receiver 4 having only output but no input can have the sameaddress as another receiver 4 having only input and no output.

(4) The number of pulses in each frame can be varied by the masterstation so that, for instance, those receivers 4 with lower addressescan be addressed more frequently than those of higher addresses.

(5) If a particular receiver 4 is to have more than one input and/oroutput then that receiver must be responsive to more than one addressallowing for independent control of the inputs and outputs. Forinstance, if a receiver 4 has eight inputs and four outputs the receivermust respond to at least eight different addresses. The inputs andoutputs do not necessarily have to have the same addresses at aparticular receiver.

(6) There are two methods to transmit analog signals in the system. Onemethod, referred to in paragraph 5 above, involves conversion of theanalog signal to digital signals before transmission and aftertransmission reconverts the digital signals back to analog signals.Another method which only requires one address per analog signal insteadof multiple addresses, is to vary the current drawn from the currentsource 36 in proportion to an analog signal generated at particularreceivers being addressed, rather than the discrete value. For instance,a current of value I may represent an analog value of zero and 8I torepresent the maximum analog value. Therefore the analog signal wouldcause the current to vary between I and 8I. For the master station 2 totransmit analog signals to the receivers 4, it can vary the duration inwhich the bus 6 is at V₂. For instance, a time duration of 0.3millisecond could represent an analog signal of zero and 1 millisecondto represent the maximum analog value. Therefore the analog signal wouldcause the time duration to vary between 0.3 to 1 millisecond.

(7) In certain applications, where there are many devices which requiremultiple addresses per device, a set of addresses can be set aside toselect a device and another set of addresses for the transmission ofdata between master station 2 and all the devices. This greatly reducesthe number of addresses required to communicate between the masterstation and the devices.

(8) The master station can be arranged such that it allows for certainvariations in the current reading from the current monitor 40 before itincorrectly interprets the signal from the receivers 4. In the preferredarrangement the variation is I/2.

(9) The pulses used for resetting, addressing and signalling could berealized by pulses of different frequencies, the resulting operationbeing analogous.

Many further modifications will be apparent to those skilled in the artwithout departing from the spirit and scope of the invention. One suchmodification is to mix the bus signal with other signals, such as cableTV signals, to be added to the system.

I claim:
 1. An electrical control system comprising:a master station anda plurality of receiver stations connected thereto by a bus; saidmastser station including generating means for generating controlsignals which are applied to said bus and to which said receiverstations are responsive; said control signals comprising a repetitiveseries of signal frames, each signal frame including a reset pulse and aplurality of address pulses; said master station also including controlmeans which can cause selectable alteration of the duration of anyaddress pulse and also the period between successive address pulses;said receiver stations being respectively addressed in a frame followingreceipt of a predetermined number of said address pulses after the resetpulse; the addressed receiver stations being responsive to the durationof the address pulse by which it is addressed whereby output informationcan be transmitted from the master station to the receiver station thusaddressed; the receiver stations including return signal generatingmeans for generating return signals which vary the impedance of the bus;said master station also including measuring means coupled to the busfor measuring the variation of the impedance of the bus; and the resetpulse of each signal frame being distinguishable from the other pulsesthereof by virtue of its relatively long duration, the outputinformation being determined by the duration of the period betweensuccessive address pulses and the return signals are generated byvarying the bus impedance by the addressed receiver station during thesame period that the receiver is addressed, whereby the master stationcan transmit output information to an addressed receiver station byvarying the duration of the period between successive pulses andsimultaneously measure the variation of the bus impedance which definesthe return signal generated by the addressed receiver.
 2. A system asclaimed in claim 1, wherein:said bus comprises of a minimum of twowires; said pulses comprise of voltage pulses on a non-zero datum; saidvoltage pulses can provide power for at least some of the receiverstations; said output information is determined by the period the bus isat the said non-zero datum voltage; said return signals comprise ofvarying bus impedance during the period the bus is at the said non-zerodatum voltage.
 3. A system as claimed in claim 1, wherein:said buscomprises a minimum of two wires; said pulses comprises of voltagepulses on a non-zero datum; said voltage pulses can provide power for atleast some of the receiver stations; said output information isdetermined by the number of zero volt pulses during the period betweensaid other voltage pulses; said return signals comprise of varying busimpedance during the period the bus is at the said non-zero volt datum.4. An electrical control system comprising:a master station and aplurality of receiver stations connected thereto by a two-wire bus; saidmaster station including generating means for generating control signalswhich are applied to said two-wire bus and to which said receiverstations are responsive; said control signals comprising a repetitiveseries of signal frames, each signal frame including a reset pulse and aplurality of address pulses; said master station also including controlmeans which can cause selectable alteration of the duration of anyaddress pulse and also the period between successive address pulses;said receiver stations being respectively addressed in a frame followingreceipt of a predetermined number of said address pulses after the resetpulse; the addressed receiver stations being responsive to the durationof the address pulse by which it is addressed whereby output informationcan be transmitted from the master station to the receiver station thusaddressed; the receiver stations including return signal generatingmeans for generating return signals which vary the impedance of thetwo-wire bus; said master station also including measuring means coupledto the two-wire bus for measuring the variation of the impedance of thebus; and the reset pulse of each signal frame being distinguishable fromthe other pulses thereof by virtue of its relatively long duration, theoutput information being determined by the duration of the periodbetween successive address pulses and the return signals are generatedby varying the bus impedance by the addressed receiver station duringthe same period that the receiver is addressed, whereby the masterstation can transmit output information to an addressed recevier stationby varying the duration of the period between successive pulses andsimultaneously measure the variation of the bus impedance which definesthe return signal generated by the addressed receiver.
 5. A system asclaimed in claim 4, wherein:said pulses comprise of voltage pulses on anon-zero datum; said voltage pulses can provide power for at least someof the receiver stations; said output information is determined by theperiod the bus is at the said non-zero datum voltage; said returnsignals comprise of varying bus impedance during the period the bus isat the said non-zero datum voltage.
 6. A system as claimed in claim 4,wherein:said pulses comprises of voltage pulses on a non-zero datum;said voltage pulses can provide power for at least some of the receiverstations; said output information is determined by the number of zerovolt pulses during the period between said other voltage pulses; saidreturn signals comprise of varying bus impedance during the period thebus is at the said non-zero volt datum.